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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7750 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1997 product-to-frequency converter functional block diagram delay 2.5v band gap reference dtf hpf mult s1 fs vdd dgnd dtf lpf 2nd order modulator agnd refout g1 adc1 adc2 refin v 1+ AD7750 2nd order modulator x2 x16 v 2+ s2 v 1C v 2C f2 clkout f1 f out revp clkin acdc features two differential analog input channels product of two channels voltage-to-frequency conversion on a single channel real power measurement capability < 0.2% error over the range 400% ibasic to 2% ibasic two or four quadrant operation (positive and negative power) gain sel ect of 1 or 16 on the current channel (channel 1) choice of on-chip or external reference choice of output pulse frequencies available (pins f1 and f2) high frequency pulse output for calibration purposes (f out ) hpf on current channel for offset removal single 5 v supply and low power general description the AD7750 is a product-to-frequency converter (pfc) that can be configured for power measurement or voltage-to- frequency conversion. the part contains the equivalent of two channels of a/d conversion, a multiplier, a digital-to-frequency converter, a reference and other conditioning circuitry. channel 1 has a differential gain amplifier with selectable gains of 1 or 16. channel 2 has a differential gain amplifier with a gain of 2. a high- pass filter can be switched into the signal path of channel 1 to remove any offsets. the outputs f1 and f2 are fixed width (275 ms) logic low going pulse streams for output frequencies less than 1.8 hz. a range of output frequencies is available and the frequency of f1 and f2 is proportional to the product of v 1 and v 2 . these outputs are suitable for directly driving an electromechanical pulse counter or full stepping two phase stepper motors. the outputs can be configured to represent the result of four-quadrant multi- plication (i.e., sign and magnitude) or to represent the result of a two quadrant multiplication (i.e., magnitude only). in this configuration the outputs are always positive regardless of the input polarities. in addition, there is a reverse polarity indicator output that becomes active when negative power is detected in the magnitude only mode, see reverse polarity indicator. the error as a percent (%) of reading is less than 0.3% over a dynamic range of 1000:1. the AD7750 is fabricated on 0.6 m cmos technology; a pro- cess that combines low power and low cost. product highlights 1. the part can be configured for power measurement or voltage-to-frequency conversion. 2. the output format and maximum frequency is selectable; from low-frequency outputs, suitable for driving stepper motors, to higher frequency outputs, suitable for calibration and test. 3. there is a reverse polarity indicator output that becomes active when negative power is detected in the magnitude only mode. 4. error as a % of reading over a dynamic range of 1000:1 is < 0.3%.
C2C rev. 0 AD7750Cspecifications (v dd = 5 v 6 5%, agnd = 0 v, dgnd = 0 v, refin = +2.5 v, clkin = 3.58 mhz t min to t max = C40 8 c to +85 8 c, acdc = logic high) a version C40 8 c to parameter +85 8 c units test conditions/comments accuracy measurement error 1 channel 2 with full-scale signal gain = 1 0.2 % reading max measured over a dynamic range on channel 1 of 500:1 0.3 % reading max measured over a dynamic range on channel 1 of 1000:1 gain = 16 0.2 % reading max measured over a dynamic range on channel 1 of 500:1 0.4 % reading max measured over a dynamic range on channel 1 of 1000:1 phase error between channels clkin = 3.58 mhz, line frequency = 50 hz phase lead 40 (pf = +0.8) 0.2 degrees ( ) max hpf filter on, acdc = 1 phase lag 60 (pf = C0.5) 0.2 degrees ( ) max hpf filter on, acdc = 1 feedthrough between channels hpf filter on, acdc = 1, mode 3, channel 1 = 0 v output frequency variation (f out ) 0.0005 % full-scale max channel 2 = 500 mv rms at 50 hz power supply rejection hpf filter on, acdc = 1, mode 3, channel 1 = 0 v output frequency variation (f out ) 0.03 % full-scale max channel 2 = 500 mv rms, power supply ripple 250 mv at 50 hz. see figures 1 and 3. analog inputs maximum signal levels 1 v max on any input, v 1+ , v 1C , v 2+ and v 2C . see analog in puts. input impedance (dc) 400 k w min clkin = 3.58 mhz bandwidth 3.5 khz typ clkin = 3.58 mhz, clkin/1024 offset error 10 mv typ gain error 4 % full-scale typ gain error match 0.3 % full-scale typ reference input ref in input voltage range 2.7 v max 2.5 v + 8% 2.3 v min 2.5 v C 8% input impedance 50 k w min on-chip reference nominal 2.5 v reference error 200 mv max temperature coefficient 55 ppm/ c typ clkin input clock frequency 4.5 mhz max 2 mhz min logic inputs fs, s1, s2, acdc and g1 input high voltage, v inh 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 v max v dd = 5 v 5% input current, i in 10 m a max typically 10 na, v in = 0 v to v dd input capacitance, c in 10 pf max clkin input high voltage, v inh 4 v min input low voltage, v inl 0.4 v max logic outputs 2 f1 and f2 output high voltage, v oh i source = 8 ma 4.3 v min v dd = 5 v output low voltage, v ol i sink = 8 ma 0.5 v max v dd = 5 v f out and revp output high voltage, v oh i source = 1 ma 4 v min v dd = 5 v 5% output low voltage, v ol i sink = 200 m a 0.4 v max v dd = 5 v 5% high impedance leakage current 10 m a max high impedance capacitance 15 pf max
C3C rev. 0 AD7750 ordering guide temperature package package model range description options AD7750an C40 c to +85 c 20-lead plastic dip n-20 AD7750ar C40 c to +85 c 20-lead wide body soic r-20 a version C40 8 c to parameter +85 8 c units test conditions/comments power supply for specified performance, digital input @ agnd or v dd v dd 4.75 v min 5 v C 5% 5.25 v max 5 v + 5% i dd 5.5 ma max typically 3.5 ma notes 1 see plots in typical performance graphs. 2 external current amplification/drive should be used if higher current source and sink capabilities are required, e.g., bipolar transistor. all specifications subject to change without notice. timing characteristics 1, 2 parameter a version units test conditions/comments t 1 3 275 ms f1 and f2 pulsewidth (logic low) t 2 see table i s output pulse period. see table i to determine the output frequency t 3 t 2 /2 s time between f1 falling edge and f2 falling edge t 4 3 90 ms f out pulsewidth (logic high) t 5 see table i s f out pulse period. see table i to determine the output frequency t 6 clkin/4 s minimum time between f1 and f2 pulse notes 1 sample tested during initial release and after any redesign or process change that may affect this parameter. 2 see figure 18. 3 the pulsewidths of f1, f2 and f out are not fixed for higher output frequencies. see the digital-to-frequency converter (dtf) section for an explanation. specifications subject to change without notice. (v dd = 5 v, agnd = 0 v, dvdd = 0 v, refin = refout. all specifications t min to t max unless otherwise noted.) absolute maximum ratings* (t a = +25 c unless otherwise noted) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v analog input voltage to agnd v 1+ , v 1C , v 2+ and v 2C . . . . . . . . . . . . . . . . . . . . C6 v to +6 v reference input voltage to agnd . . . . C0.3 v to v dd + 0.3 v digital input voltage to dgnd . . . . . . C0.3 v to v dd + 0.3 v digital output voltage to dgnd . . . . . C0.3 v to v dd + 0.3 v operating temperature range commercial (a version) . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7750 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device 20-lead soic package, power dissipation . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 74 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c 20-lead plastic dip, power dissipation . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 102 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AD7750 C4C rev. 0 pin function descriptions pin no. mnemonic descriptions 1v dd power supply pin, 5 v nominal 5% for specifications. 2 g1 gain select, digital input. this input selects the gain for the channel 1 differential input. when g1 is low, the gain is 1 and when g1 is high, the gain is 16. see analog inputs section. 3, 4 v 1(+) , v 1(C) channel 1 differential inputs. see the analog inputs section for an explanation of the maximum input signal ranges. channel 1 has selectable gains of 1 and 16. the absolute maximum rating is 6 v for each pin. the recommended clamp voltage for external protection circuitry is 5 v. 5 agnd the analog ground reference level for channels 1 and 2 differential input voltages. absolute voltage range relative to dgnd pin is C20 mv to +20 mv. the analog ground of the pcb should be connected to digital ground by connecting the agnd pin and dgnd pin together at the dgnd pin. 6, 7 v 2(+) , v 2(C) channel 2 differential inputs. see the analog inputs section for an explanation of the maximum input signal ranges. channel 2 has a fixed gain of 2. the absolute maximum rating is 6 v for each pin. the recommended clamp voltage for external protection circuitry is 5 v. 8 refout internal reference output. the AD7750 can use either its own internal 2.5 v reference or an external reference. for operation with the internal reference this pin should be connected to the refin pin. 9 refin reference input. the AD7750 can use either its own internal 2.5 v reference or an external reference. for operation with an external reference, a 2.5 v 8%, reference should be applied at this pin. for op- eration with an internal reference, the refout pin should be connected to this input. for both internal or external reference connections, an input filtering capacitor should be connected between the refin pin and analog ground. 10 dgnd the ground and substrate supply pin, 0 v. this is the reference ground for the digital inputs and out- puts. these pins should have their own ground return on the pcb, which is joined to the analog ground reference at one point, i.e., the dgnd pin. 11 fs frequency select, digital input. this input, along with s1 and s2, selects the operating mode of the AD7750see table i. 13, 12 s1, s2 mode selection, digital inputs. these pins, along with fs, select the operating mode of the AD7750 see table i. 14 acdc high-pass filter control digital input. when this pin is high, the high-pass filter is switched into the signal path of channel 1. when this pin is low, the high-pass filter is removed. note when the filter is off there is a fixed time delay between channels; this is explained in the functional description section. 15 clkin an external clock can be provided at this pin. alternatively, a crystal can be connected across clkin and clkout for the clock source. the clock frequency is 3.58 mhz for specified operation. 16 clkout when using a crystal, it must be connected across clkin and clkout. the clkout can drive only one cmos load when clkin is driven externally. 17 revp reverse polarity, digital output. this output becomes active high when the polarity of the signal on channel 1 is reversed. this output is reset to zero at power-up. this output becomes active only when there is a pulse output on f1 or f2. see reverse polarity indicator section. 18 f out high-speed frequency output. this is also a fixed-width pulse stream that is synchronized to the AD7750 clkin. the frequency is proportional to the product of channel 1 and channel 2 or the signal on either channel, depending on the operating modesee table i. the output format is an active high pulse approximately 90 ms widesee digital-to-frequency conversion section. 20, 19 f1, f2 frequency outputs. f1 and f2 provide fixed-width pulse streams that are synchronized to the AD7750 clkin. the frequency is proportional to the product of channel 1 and channel 2see table i. the output format is an active low pulse approximately 275 ms widesee digital-to-frequency conver- sion s ection.
AD7750 C5C rev. 0 pin configuration soic and dip 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD7750 v dd revp f out f2 f1 g1 v 1+ v 1 acdc clkin clkout agnd v 2+ v 2 refout refin dgnd fs s2 s1 typical performance characteristics 50hz ripple ?v rms 140 0 0 0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 120 80 60 40 20 100 as per data sheet conditions with gain = 1 dbs figure 1. psr as a function of v dd 50 hz ripple line frequency ?hz 0.6 ?.8 45 53 46 47 48 49 50 51 52 0.4 0 ?.2 ?.4 ?.6 0.2 54 55 degrees figure 2. phase error as a function of line frequency 50hz ripple ?v rms 120 0 0.08 0.01 0.02 0.03 0.04 0.05 0.06 0.07 100 60 40 20 0 80 as per data sheet conditions with gain = 16 0.09 dbs figure 3. psr as a function of v dd 50 hz ripple
AD7750 C6C rev. 0 v1 amplitude C mv rms 0.1 0.001 0.01 0.1 1.0 10 0.05 C0.05 C0.1 C0.15 C0.2 0 C0.25 C0.3 error C % of reading v dd = 5v v2 = full scale figure 4. error as a percentage (%) of reading over a dynamic range of 1000, gain = 1 v1 amplitude C mv rms 0.0001 0.01 0.1 0 0.001 C0.05 C0.1 C0.15 C0.2 C0.25 C0.3 C0.35 C0.4 C0.45 C0.5 error C % of reading v dd = 5v v2 = full scale figure 5. error as a percentage (%) of reading over a dynamic range of 1000, gain = 16 v1 amplitude C mv rms 0.2 10 0 C0.2 C0.4 0 C0.6 10 1 10 2 10 3 0.4 0.6 error C % of reading v dd = 5.25v v dd = 5.00v v dd = 4.75v figure 6. measurement error vs. input signal level and varying v dd with channel 1, gain = 1 v1 amplitude C mv rms 0.2 10 C2 C0.4 C0.6 0 10 C1 10 0 10 2 0.4 0.6 error C % of reading v dd = 5.25v v dd = 5.00v v dd = 4.75v C0.2 0.8 10 1 figure 7. measurement error vs. input signal level and varying v dd with channel 1, gain = 16
AD7750 C7C rev. 0 analog inputs the analog inputs of the AD7750 are high impedance bipolar voltage inputs. the four voltage inputs make up two truly differential voltage in put channels called v 1 and v 2 . as with any adc, an antialiasing filter or low-pass filter is required on the analog input. the AD7750 is designed with a unique switched capacitor architecture that allows a bipolar analog input with a single 5 v power supply. the four analog inputs (v 1+ , v 1C , v 2+ , v 2C ) each have a voltage range from C1.0 v to +1.0 v. this is an absolute voltage range and is relative to the ground (agnd) pin. this ground is nominally at a potential of 0 v relative to the board level ground. figure 8 shows a very simplified diagram of the analog input structure. when the ana- log input voltage is sampled, the switch is closed and a very small sampling capacitor is charged up to the input voltage. the resistor in the diagram can be thought of as a lumped compo- nent made up of the on resistance of various switches. v in r 1.4k v c 2pf sampling capacitor figure 8. equivalent analog input circuit analog inputs protection circuitry the analog input section also has protection circuitry. since the power supply rails are 0 v to 5 v, the analog inputs can no longer be clamped to the supply rails by diodes. thus, the inter- nal protection circuitry monitors the current paths during a fault condition and protects the device from continuous overvoltage, continuous undervoltage and esd events. the maximum over- voltage the AD7750 analog inputs can withstand without caus- ing irreversible damage is 6 v relative to agnd pin. in the case of continuous overvoltage and undervoltage the series resistance of the antialiasing filter can be used to limit input current. the total input current in the case of a fault should be limited to 10 ma. for normal operation of the AD7750 there are two further re- strictions on the signal levels presented to the analog inputs. 1. the voltage on any input relative to the agnd pin must not exceed 1 v. 2. the differential voltage presented to the adc (analog modulator) must not exceed 2 v. in figure 12, channel 1 has a peak voltage on v 1+ and v 1C of 1 v. these signals are not gained (g1 = 0) and so the differential signal presented to the modulator is 2 v. however, channel 2 has an associated gain of two and so care must be taken to ensure the modulator input does not exceed 2 v. therefore, the maximum signal voltage that can appear on v 2+ and v 2C is 0.5 v. the difference between single-ended and complementary differential input schemes is shown in the diagram below, figure 9. for a single-ended input scheme the vC input is held at the same potential as the agnd pin. the maxi- mum voltages can then be applied to the v+ input are shown in figures 10 and 11. an example of this input scheme uses a shunt resistor to convert the line current to a voltage that is then applied to the v 1+ input of the AD7750. an example of the complementary differential input scheme uses a current transformer to convert the line current to a voltage that is then applied to v 1+ and v 1C . with this scheme the voltage on the v+ input is always equal to, but of opposite polarity to the voltage on vC. the maximum voltage that can be applied to the inputs of the AD7750 using this scheme is shown in figures 12 and 13. note that the common mode of the analog inputs must be driven. the output terminals of the ct are, therefore, referenced to ground. a current transformer provides complementary differential inputs to the AD7750 a current sense resistor provides a single-ended input to the AD7750 v+ vC vC v+ shunt resistor figure 9. examples of complementary and single- ended input schemes
AD7750 C8C rev. 0 v 1+ = 6 1v max 6 1v max v 1C = agnd 6 1v 6 2v x1 x2 adc adc dtf f out f1 f2 6 2v max v 2C = agnd v 2+ = 6 1v max figure 10. maximum input signals with respect to agnd for a single-ended input scheme, g1 = 0 v 1+ = 6 125mv max 6 2v max v 1C = agnd 6 2v 6 2v x16 x2 adc adc dtf f out f1 f2 6 2v max v 2C = agnd v 2+ = 6 1v max figure 11. maximum input signals with respect to agnd for a single-ended input scheme, g1 = 1 v+ = 6 1v max 6 1v max vC = 6 1v max 6 2v 6 2v x1 x2 adc adc dtf f out f1 f2 6 1v max 6 1v max 6 1v max vC = 6 0.5v max v+ = 6 0.5v max figure 12. maximum input signals for a complementary input scheme, g1 = 0 v+ = 6 62.5v max 6 1v max vC = 6 62.5v max 6 2v 6 2v x16 x2 adc adc dtf f out f1 f2 6 1v max 6 1v max 6 1v max vC = 6 0.5v max v+ = 6 0.5v max figure 13. maximum input signals for a complementary input scheme, g1 = 1
AD7750 C9C rev. 0 determining the output frequencies of the AD7750 f out , f1 and f2 are the frequency outputs of the AD7750. the output frequencies of the AD7750 are a multiple of a binary fraction of the master clock frequency clkin. this binary fraction of the master clock is referred to as f max in this data sheet. f max can have one of two values, f max1 and f max2 , depending on which mode of operation the AD7750 is in. the operating modes of the AD7750 are selected by the logic inputs fs, s2 and s1. the table below outlines the f max frequencies and the transfer functions for the various operating modes of the AD7750. notes 1 the variable k is proportional to the product of the rms differential input voltages on channel 1 and channel 2 (v 1 and v 2 ). k = (1.32 v 1 v 2 gain)/v ref 2 2 applies to f out only. the variable k is proportional to the instantaneous differential input voltage on channel 1 (fs = 0, s1 = 1, s0 = 1) or the instantaneous diff er- ential voltage on channel 2 (fs = 1, s1 = 1, s0 = 1), i.e., channel monitor mode. k = (0.81 v)/v ref v = v 1 gain or v = v 2 2 note: v 1 and v 2 here refer to the instantaneous differential voltage on channel 1 or channel 2, not the rms value. e d o ms f2 s1 sn o i t p i r c s e d e d o m2 f , 1 f 1 ) z h (f t u o 1 ) z h (f x a m 0000 . e d o m t n e m e r u s a e m r e w o p n o i t a c i l p i t l u m t n a r d n a u q r u o f . ) t u p t u o e d u t i n g a m d n a n g i s ( f 1 x a m f . k 1 x a m f [ . 6 1 1 x a m f . k 1 x a m ]f 1 x a m 2 / n i k l c = 9 1 f 1 x a m z h 8 . 6 = 1001 . e d o m t n e m e r u s a e m r e w o p n o i t a c i l p i t l u m t n a r d n a u q o w t . ) y l n o e d u t i n g a m ( f . k o t 0 1 x a m f . k o t 0 [ . 8 1 x a m ]f 1 x a m 2 / n i k l c = 9 1 f 1 x a m z h 8 . 6 = 2010 . e d o m t n e m e r u s a e m r e w o p n o i t a c i l p i t l u m t n a r d n a u q o w t . ) y l n o e d u t i n g a m ( f . k o t 0 1 x a m f . k o t 0 [ . 6 1 1 x a m ]f 1 x a m 2 / n i k l c = 9 1 f 1 x a m z h 8 . 6 = 3 2 011v 1 f n o e d o m r o t i n o m l e n n a h c . t u o e d o m t n e m e r u s a e m r e w o pf n o1 , . ) t u p t u o e d u t i n g a m d n a n g i s ( 2 f f 1 x a m f . k 1 x a m f [ . 2 3 1 x a m k 2 f . 1 x a m ]f 1 x a m 2 / n i k l c = 9 1 f 1 x a m z h 8 . 6 = 4100 . e d o m t n e m e r u s a e m r e w o p n o i t a c i l p i t l u m t n a r d n a u q r u o f . ) t u p t u o e d u t i n g a m d n a n g i s ( f 2 x a m f . k 2 x a m f [ . 6 1 2 x a m f . k 2 x a m ]f 2 x a m 2 / n i k l c = 8 1 f 2 x a m z h 6 . 3 1 = 5101 . e d o m t n e m e r u s a e m r e w o p n o i t a c i l p i t l u m t n a r d n a u q o w t . ) y l n o e d u t i n g a m ( f . k o t 0 2 x a m f . k o t 0 [ . 6 1 2 x a m ]f 2 x a m 2 / n i k l c = 8 1 f 2 x a m z h 6 . 3 1 = 6110 . e d o m t n e m e r u s a e m r e w o p n o i t a c i l p i t l u m t n a r d n a u q o w t . ) y l n o e d u t i n g a m ( f . k o t 0 2 x a m f . k o t 0 [ . 2 3 2 x a m ]f 2 x a m 2 / n i k l c = 8 1 f 2 x a m z h 6 . 3 1 = 7 2 111v 2 f n o e d o m r o t i n o m l e n n a h c . t u o , 1 f n o e d o m t n e m e r u s a e m r e w o p . ) t u p t u o e d u t i n g a m d n a n g i s ( 2 f f 2 x a m f . k 2 x a m f [ . 6 1 2 x a m k 2 f . 2 x a m ]f 2 x a m 2 / n i k l c = 8 1 f 2 x a m z h 6 . 3 1 = mode description (table i) the section of table i labeled mode description summarizes the functional modes of the AD7750. the AD7750 has two basic modes of operation, i.e., four and two quadrant multiplica- tion. the diagram in figure 14 is a graphical representation of the transfer functions for two and four quadrant multiplication. four quadrant multiplication (modes 0, 3, 4 and 7) when the AD7750 is operating in its four quadrant multiplica- tion mode the output pulse frequency on f1, f2 and f out contains both sign and magnitude information. the magni- tude information is indicated by the output frequency varia tion (k.f max ) from a center frequency (f max ). the sign informa- tion is indicated by the sign of the frequency variation around f max . for example if the output frequency is equal to f max C k.f max then the magnitude of the product is given by k.f max and it has a negative sign. two quadrant multiplication (modes 1, 2, 5 and 6) when operating in this mode the output pulse frequency only contains magnitude information. again as in the case of four quadrant multiplication the magnitude information is included in the output frequency variation (k.f max ). however, in this mode the zero power frequency is 0 hz, so the output frequency variation is from 0 hz to (k.f max ) hz. also note that a no-load threshold and the reverse polarity indicator are implemented in these modes see no load threshold and reverse polarity indicator sections. these modes are the most suitable for a class 1 meter implementat ion. channel monitor modes (modes 3 and 7) in this mode of operation the f out pulse frequency does not give product information. when fs = 0, the f out output fre- quency gives sign and magnitude information about the volt- age on channel 1. when fs = 1 the f out output frequency gives sign and magnitude information about the voltage on channel 2. note the f1, f2 pulse outputs still continue to give power information. table i. operating mode
AD7750 C10C rev. 0 maximum output frequencies table ii shows the maximum output frequencies of f out and f1, f2 for the various operating modes of the AD7750. the table shows the maximum output frequencies for dc and ac input signals on v 1 and v 2 . when an ac signal (sinusoidal) is applied to v 1 and v 2 the AD7750 produces an output frequency which is proportional to the product of the rms value of these inputs. if two ac signals with peak differential values of v 1max and v 2max are applied to channels 1 and 2, respectively, then the output frequency is proportional to v 1max /sqrt(2) v 2max / sqrt(2) = (v 1max v 2max )/2. if v 1max and v 2max are also the maximum dc input voltages then the maximum output frequen- cies for ac signals will always be half that of dc input signals. example calculation of f1, f2 max for mode 2 and gain = 1. the maximum input voltage (dc) on channel 1 is 2 v (v 1+ = +1 v, v 1C = C1 v)see analog inputs section. the maximum input voltage on channel 2 is 1 v. using the transfer function: k = (1.32 v 1 v 2 gain )/ v ref 2 k = 0.4224 f 1, f 2 = k .6.8 hz = 2.9 hz functional description the AD7750 combines two analog-to-digital converters, a digi- tal multiplier, digital filters and a digital-to-frequency (dtf) converter onto one low cost integrated circuit. the AD7750 is fabricated on a double poly cmos process (0.6 m ) and retains its high accuracy by performing all multiplications and manipu- lations in the digital domain. the schematic in figure 15 shows an equivalent circuit for the AD7750 signal processing chain. the first thing to notice is that the analog signals are first con- verted to digital signals by the two second-order sigma-delta modulators. all subsequent signal processing is carried out in the digital domain. the main source of errors in an application is therefore in the analog-to-digital conversion process. for this reason great care must be taken when interfacing the analog inputs of the AD7750 to the transducer. this is discussed in the applications section. hpf in channel 1 to remove any dc offset that may be present at the output modulator 1, a user selectable high-pass iir filter (pin acdc) can be introduced into the signal path. this hpf is necessary when carrying out power measurements. however, this hpf has an associated phase lead given by 90 Ctan C1 (f/2.25). figure 16 shows the transfer function of the hpf in channel 1. the phase lead is 2.58 at 50 hz. in order to equalize the phase difference between the two channels a fixed time delay is intro- duced. the time delay is set at 143 m s, which is equivalent to a phase lag of C2.58 at 50 hz. thus the cumulative phase shift through channel 1 is 0 . because the time delay is fixed, external phase compensation circ uitry will be required if the line frequency differs from 50 hz. for example with a line frequency of 60 hz the phase lead due to the hpf is 2.148 and the phase lag due to the fixed time delay is 3.1 . this means there is a net phase lag in chan- nel 1 of 0.952 . this phase lag in channel 1 can be compen- sated for by using a phase lag compensation circuit like the one shown in figure 17. the phase lag compensation is placed on channel 2 (voltage channel) to equalize the channels. the antialiasing filter associated with channel 1 (see applications section) produces a phase lag of 0.6 at 50 hz; therefore, to equalize the channels, a net phase lag of (0.6 + 0.952 ) 1.552 should be in place on channel 2. the gain trim resistor vr1 (100 w ) produces a phase lag variation of 1.4 to 1.5 with vr2 = 0 w . vr2 can add an additional 0.1 phase lag (vr2 = 200 w ). v2 (+) four quadrant multiplication (sign and magnitude) two quadrant multiplication ( magnitude only) (1.32 3 v1 3 v2 3 gain) v ref 2 k = v2(C) 0 v2(C) v2 (+) k 3 f max (+) f max + k 3 f max (+) f max C k 3 f max (C) k 3 f max (+) f max + k 3 f max (+) f max _ k 3 f max (C) k 3 f max (+) k 3 f max (+) v1(C) v1(+) v1(C) v1(+) figure 14. transfer functions (four and two quadrant multiplication)
AD7750 C11C rev. 0 table ii. maximum output frequencies h(s) = src 1 + src r c r = 1m v c = 0.0707 m f figure 16. hpf in channel 1 c1 47nf r2 33k v c2 33nf vr2 200 v r1 1m v pin 7 vr1 100 v r3 1.1k v 860:1 attenutation pin 6 r4 1.1k v c3 33 m f figure 17. phase lag compensation on channel 1 for 60 hz line frequency adc 1 pga f out f1 f2 adc 2 t v 1+ v 1C v 2+ v 2C x2 g1 acdc hpf phase lead of 2.58 8 c at 50hz digital multiplier lpf clkin fs s2 s1 time delay 143 m s (clkin = 3.5795mhz) 2.58 8 c at 50hz digital-to-frequency block counter/accumulator dtf figure 15. equivalent AD7750 signal processing chain e d o ms f2 s1 s ) z h ( 2 f , 1 f ) c d ( f t u o ) z h ( ) c d ( ) z h ( 2 f , 1 f ) c a ( f t u o ) z h ( ) c a ( 0000 9 . 2 8 . 66 4 9 0 15 4 . 1 8 . 63 2 9 0 1 1001 9 . 2 o t 03 2 o t 05 4 . 1 o t 05 . 1 1 o t 0 2010 9 . 2 o t 06 4 o t 05 4 . 1 o t 03 2 o t 0 3011 9 . 2 8 . 62 4 1 8 1 25 4 . 1 8 . 62 4 1 8 1 2 4100 8 . 5 6 . 3 12 9 8 1 29 . 2 6 . 3 16 4 8 1 2 5101 8 . 5 o t 02 9 o t 09 . 2 o t 06 4 o t 0 6110 8 . 5 o t 04 8 1 o t 09 . 2 o t 02 9 o t 0 7111 8 . 5 6 . 3 12 4 1 8 1 29 . 2 6 . 3 12 4 1 8 1 2 digital-to-frequency converter (dtf) after they have been filtered, the outputs of the two sigma-delta modulators are fed into a digital multiplier. the output of the multiplier is then low-pass filtered to obtain the real power information. the output of the lpf enters a digital-to-frequency converter whose output frequency is now proportional to the real power. the dtf offers a range of output frequencies to suit most power measurement applications. there is also a high frequency output called f out , which can be used for calibra- tion purposes. the output frequencies are determined by the logic inputs fs, s2 and s1. this is explained in the section of this data sheet called determining the output frequencies of the AD7750. figure 18 shows the waveforms of the various frequency out- puts. the outputs f1 and f2 are the low frequency outputs that can be used to directly drive a stepper motor or electrome- chanical pulse counter. the f1 and f2 outputs provide two alternating low going pulses. the pulsewidth is set at 275 ms and the time between the falling edges of f1 and f2 is ap- proximately half the period of f1. if, however, the period of f1 and f2 falls below 550 ms (1.81 hz) the pulsewidth of f1 and f2 is set to half the period. for example in mode 3, where f1 and f2 vary around 6.8 hz, the pulsewidth would vary from 1/2.(6.8+1.45) seconds to 1/2.(6.8C1.45) secondssee table ii.
AD7750 C12C rev. 0 1 see iec 1036 2nd edition 1996-09 section 3.5.1.1. the high frequency f out output is intended to be used for communications (via ir led) and calibration purposes. f out produces a 90 ms wide pulse at a frequency that is proporti onal to the product of channel 1 and channel 2 or the instanta- neous voltage on channel 1 or channel 2. the output fre- quencies are given in table i in the determining the output frequencies of the AD7750 section of this data sheet. as in the case of f1 and f2, if the period of f out falls below 180 ms, the f out pulsewidth is set to half the period. for example, if the f out frequency is 20 hz, the f out pulsewidth is 25 ms. f1 f2 f out t 1 v dd 0v v dd v dd 0v 0v t 6 t 2 t 3 t 4 t 5 figure 18. timing diagram for frequency outputs voltage reference the AD7750 has an on-chip temperature compensated band- gap voltage reference of 2.5 v with a tolerance of 250 mv. the temperature drift for the reference is specified at 50 ppm/ c. it should be noted that this reference variation will cause a frequency output variation from device to device for a given set of input signals. this should not be a problem in most applica- tions since it is a straight gain error that can easily be removed at the calibration stage. reverse polarity indicator when the AD7750 is operated in a magnitude only mode of operation (i.e., modes 1, 2, 5 and 6), and the polarity of the power changes, the logic output revp will go high. however, the revp pin is only activated when the there is pulse output on f1 or f2. therefore, if the power being measured is low, it may be some time before the revp pin goes logic high even though the polarity of the power is reversed. once activated the revp output will remain high until the AD7750 is powered down. applications information designing a single phase class 1 energy meter (iec 1036) the AD7750 product-to-frequency converter is designed for use in a wide range of power metering applications. in a typical power meter two parameters are measured (i.e., line voltage and current) and their product obtained. the real power is then obtained by low-pass filtering this product result. the line voltage can be measured through a resistor divider or voltage transformer, and the current can be sensed and converted to a voltage through a shunt resistor, current transformer or hall effect device. the design methodology used in the following example is to use the upper end of the current channel dynamic range, i.e., chan- nel 1 of the AD7750. the assumption here is that the signal on the voltage channel will remain relatively constant while the signal on the current channel will vary with load. using the upper end of the dynamic range of channel 1 will improve the meter accuracy with small load currents. hence an error of less than 1% from 4% ib to 400% ib will be easier to achieve. we will assume the design of a class 1 meter. the specification (iec1036) requires that the meter have an error of no greater than 1% over the range 4% ib to 400% ib (i max ), where ib is the basic current 1 . in addition, we will design a meter that ac- commodates signals with a crest factor of 2. the crest factor is the ratio of v peak /v rms. a pure sinusoidal waveform has a crest of sqrt(2) = 1.414 and an undistorted triangular waveform has a crest factor of sqrt(3) = 1.73. using a gain of 1 on channel 1 the maximum differential signal which can be applied to chan- nel 1 is 2 vsee analog input ranges section. with a crest factor of 2 the maximum rms signal on channel 1 is, therefore, 1 v rms (equivalent to i max ). the smallest signal (4% ib) ap- pearing on channel 1 is therefore 10 mv rms. load current channel 1 4% ib 10 mv rms ib 250 mv rms 400 ib 1 v rms 2 0. 2 0. 02 0. 002 1 0.01 400% ib 4% ib channel 1 input signal C vrms figure 19. use the upper end of the dynamic range of channel 1 (current) calculations for a 100 ppkwhr meter the AD7750 offers a range of maximum output frequencies see table i and table ii. in the magnitude only modes of oper ation the two maximum output frequencies are 1.45 hz and 2.9 hz. the signal on the voltage channel (channel 2) is scaled to achieve the correct output pulse frequency for a given load (e.g., 100 ppkwhr). the relationship between the input signals and the output frequency is given by the equation: freq = k f max where k = (1.32 v 1 v 2 gain )/ v ref 2 f max = 6.8 hz or 13.6 hz depending on the modesee table i, gain is the gain of channel 1, v 1 and v 2 are the differential voltages on channels 1 and 2 and v ref is the reference voltage (2.5 v 8%). to design a 100 ppkwhr meter with ib = 15 a rms and a line voltage of 220 v rms the output pulse frequency with a load current of ib is 0.0916 hz (see calculation 1 below). therefore, 0.0916 hz = k 6.8 hz (mode 2) or k = 0.01347. with a load current of ib the signal on channel 1 (v 1 ) is equal to 0.25 v rms (remember 400% ib = 1 v rms) and, therefore, the signal on channel 2 (v 2 ) is equal to 0.255 v rms (see calcula- tion 2). this means that the nominal line voltage (220 v rms) needs to be attenuated by approximately 860, i.e., 220/0.255.
AD7750 C13C rev. 0 for 100 ppkwhr v 2 is equal to 0.255 v rms or the line volt- age attenuated by a factor of 860. calculation 1 100 ppkwhr = 0.02777 hz/kw. ib of 15 a rms and line voltage of 220 v = 3.3 k w . hence, the output frequency is given by 3.3 0.02777 hz = 0.0916 hz. calculation 2 k = (1.32 v 1 v 2 gain)/v ref 2 . 0.01347 = (1.32 0.25 v 2 1)/6.25. v 2 = 0.255. figure 21 below shows how the design equations from the previ- ous page are implemented. measuring the load current the load current is converted to a voltage signal for channel 1 using a ct (current transformer). a 15 a rms load should produce a 250 mv rms signal on channel 1. a ct with a turns ratio of 120 and a shunt resistor of 2 w . will carry out the neces- sary current to voltage conversion. the ct and its shunt resis- tance should be placed as close as possible to the AD7750. this will improve the accuracy of the meter at very small load cur- rents. at small load currents the voltage levels on channel 1 are in the order of 10 mv and the meter is more prone to error due to stray signal pick up. when measuring power the hpf in the current channel must be switched on. this is done by con- necting the acdc pin to v dd . note: the voltage signals on v 1+ and v 1C must be referenced to ground. this can be achieved as shown in figure 21 below, i.e., by referencing 1/2 r ct to ground or by connecting a centertap on the ct secondary to ground. measuring the line voltage when the AD7750 is biased around the live wire as shown in figure 21, the task of measuring the line voltage is greatly simplified. a resistor divider attenuates the line voltage and provides a single-ended input for channel 2. the component values of the divider are chosen to give the correct rating (e.g., 100 ppkwhr) for the meter. see the design equations on the previous page. for this design an attenuation ratio of 860:1 is required. antialiasing components channels 1 and 2 the AD7750 is basically two adcs and a digital multiplier. as with any adc, a lpf (low-pass filter) should be used on the analog inputs to avoid out of band signal being aliased into the band of interest. in the case of a class 1 meter the band of interest lies in the range 48 hz to 1 khz approximately. the components r3, r4, r6, r7, c5, c6, c9 and c10 make up the lpfs on each of the four analog inputs. note that although channel 2 is used single ended a lpf is still required on v 2C . power supply circuit the AD7750 operates from a single power supply of 5 v 5% but still accommodates input signals in the range 1 v. because the AD7750 doesnt require dual supplies the number of exter- nal components for the power supply is reduced. one of the most important design goals for the power supply is to ensure that the ripple on the output is as low as possible. every analog or mixed signal ic is to a greater or lesser extent susceptible to power supply variations. power supply variations or ripple, if large enough, may affect the accuracy of the device when mea- suring small signals. the plot in figure 20 shows the ripple associated with the circuit in figure 21. the ripple is in the region of 10 mv peak to peak. time 2 ms 5.065 5.060 5.050 600 620 volts 5.055 640 660 680 700 720 740 760 780 800 figure 20. power supply ripple c1 ct 120:1 r1 *biasing around the live wire patented by schlumberger. xtal 3.57954mhz c2 r2 z1 d1 r4 r3 c5 c6 1/2 r ct 1 v r6 v dd c9 c10 c12 c11 c8 c7 mov source load d2 d3 d4 r7 r8 r9 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD7750 m mode2 v dd v dd v dd * 1/2 r ct 1 v vr1 r5 pulse counter ir diode for calibration reverse polarity indicator d5 c4 c3 phase neutral figure 21. suggested class 1 meter implementation
AD7750 C14C rev. 0 registering the power output the low frequency pulse outputs (f1 and f2) of the AD7750 provide the frequency output from the product-to-frequency conversion. these outputs can be used to drive a stepper motor or impulse counter. a high frequency output is available at the pin f out . this high frequency output is used for calibration purposes. in mode 2 the output frequency is 16 f1(2). with a load current of ib the frequency at f out will be 1.4656 hz (0.0916 hz 16 from calculations). if a higher frequency output is required, the fs pin can be set to v dd 5 v for calibration. in this case the output frequency is equal to 64 f1 or 5.8624 hz at ibsee table i. no load threshold of the AD7750 the AD7750 will detect when the power drops below a certain level. when the power (current) drops below a predefined threshold the AD7750 will cease to generate an output drive for the stepper motor (f1, f2). this feature of the AD7750 is intended to reproduce the behavior of ferraris meters. a ferraris meter will have friction associated with the wheel rota- tion, therefore the wheel will not rotate below a certain power level. the no load threshold is only implemented in the magni- tude only modes (modes 1, 2, 5 and 6see table i). the iec1036 specification includes a test for this effect by requiring no output pulses during some predetermined time period. this time period is calculated as: time period = 60,000 /pulses-per-minute if a meter is calibrated to 100 ppkwhr with a f out running 16 times faster than f1 and f2, this time period is 37.5 minutes (60,000/1,600). the iec1036 specifications state that the no load threshold must be less than the start up current level. this is specified as 0.4% of ib. the threshold level for a given design can be easily calculated given that the minimum output frequency of the AD7750 is 0.00048% of the maximum output frequency for a full-scale differential dc input. for example if fs = 0, the maximum output frequency for a full-scale dc input is 2.9 hz (see table ii) and the minimum output frequency is, therefore, 1.39 10 C5 hz. calculating the threshold power (current) the meter used in this example is calibrated to 100 ppkwhr, has an ib (basic current) of 15 a rms, the line voltage is 220 v rms and the turns ratio of the ct on channel 1 is 120:1 with an 2 w shunt resistor. the nominal voltage on channel 2 of the AD7750 is 255 mv rms. an f max of 6.8 hz is selected by setting fs = 0. a magni- tude only mode (mode 2) is selected to enable the no load thresh- old. the gain on channel 1 is set to 1. the threshold power or current can be found by using the transfer function in table i. f1, f2 = (1.32 v 1 v 2 gain f max )/v ref 2 from the transfer function v 1 is calculated as 37.95 m v rms see calculation 3. this is equivalent to a line current of: (37.95 m v/ 2 w ) 120 = 2.27 ma rms or 0.5 w or (2.27 ma/ 15 a) 100% = 0.015% of ib . note: the no load threshold as a percentage of ib will be different for each value of ib since the no load in watts is fixed: fs = 0, the no load threshold is (f max = 6.8 hz) 0.5 watts for a 100 ppkwhr meter 5 watts for a 10 ppkwhr meter fs = 1, the no load threshold is (f max = 13.6 hz) 1 watt for a 100 ppkwhr meter 10 watts for a 10 ppkwhr meter calculation 3 f min = 1.32 v 1 v 2 gain 6.8 hz) v ref 2 1.39 10C5 hz = v 1 0.2555 1 6.8)/6.25 v 1 = 37.95 m v external lead/lag compensation external phase compensation is often required in a power meter design to eliminate the phase errors introduced by transducers and external components. the design restriction on any external compensating network is that the network must have an overall low-pass response with a 3 db point located somewhere between 5 khz and 6 khz. the corner frequency of this lpf(s) is much higher than the band of interest. the reason for this is to mini- mize its effect on phase variation at 50 hz due to component tolerances. with the antialiasing filters on all channels having the same corner (C3 db) frequency, the main contribution to phase error will be due to the ct. a phase lead in a channel is compensated by lowering the corner frequency of the antialiasing filter to increase its associated lag and therefore cancel the lead. a phase lag in a channel should be compensated by introducing extra lag in the other channel. this can be done as previously described, i.e., moving the corner frequency of the antialiasing filters. the result in this case is that the signal on both channels has the same amount of phase lag and is therefore in phase at the analog inputs to the AD7750. the recommended rc values for the antialiasing filters on the voltage and current channels (see antialiasing components channels 1 and 2) are r = 1 k w , c = 33 nf and r = 100 w , c = 330 nf respectively. these values produce a phase lag of 0.6 through the filters. varying r in the antialiasing network from 80 w to 100 w or 800 w to 1 k w produces a phase variation from 0.475 to 0.6 at 50 hz. this allows the user to vary the lag by 0.125 .
AD7750 C15C rev. 0 table iii. components for suggested class 1 meter implementation in figure 21 schematic designator description comments r1 470 w , 5%, 1 w r2 1 k w , 5%, 1/2 w r3, r4, 100 w , 10%, 1/2 w these registers are required to form part of the antialiasing filtering on the analog inputs; r7 1 k w , 10%, 1/2 w they do not perform a voltage-to-current conversion. r5 1 m w , 5%, 2 w the choice of r5 determines the attenuation on the voltage channels and hence the meter rating, e.g., 100 ppkwhr. r6 1.1 k w , 5%, 1/2 w forms part of the gain calibration network with r5 and vr1. r8, r9 500 w , 10%, 1/2 w vr1 100 w , 10/15 turn this potentiometer is used to perform the gain calibration of the meter. attenuation of 830 to 900see applications section. c1 470 nf, 250 v ac c2 100 m f, 24 v dc c3, c4 33 pf c5, c6, 330 nf forms part of the antialiasing filters on the analog inputs. c9, c10 33 nf c7, c11 10 m f, 10 v c8, c12 10 nf z1 1n750 d1, d2 1n4007 d3 led d4, d5 ir leds xtal 3.579545 mhz mov v250pa40a metal oxide varistorCharris semiconductor.
AD7750 C16C rev. 0 outline dimensions dimensions shown in inches and (mm). c3156C8C10/97 printed in u.s.a. 20-lead plastic dip (n-20) 20 110 11 1.060 (26.90) 0.925 (23.50) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 20-lead wide body soic (r-20) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 20 11 10 1 0.5118 (13.00) 0.4961 (12.60) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1

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